1. Field of the Invention
The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to memory device with a deep trench capacitor.
2. Description of Related Art
Along with the miniaturization of devices, the dimensions of devices progressively diminish. As for a memory device that comprises a capacitor, the space for forming a capacitor also gradually reduces. A deep trench capacitor memory device which uses the space in the substrate to form a capacitor to render a greater area. A deep trench capacitor memory device thus conforms to the demands of the current market.
A conventional fabrication method for a deep trench capacitor memory device includes depositing multi layers of doped polysilicon layer to form an upper electrode. The upper most doped polysilicon layer is formed by forming a layer of non-crystalline silicon layer, followed by delivering an arsenic gas into the reaction chamber for arsenic to be adsorbed onto the non-crystalline silicon layer. An undoped polysilicon layer is further deposited. Thereafter, in a subsequent thermal process, dopants are driven-in to the undoped polysilicon layer to transform the non-crystalline silicon layer into a polysilicon layer.
In the above conventional method, during the diffusion of the arsenic ions that are being adsorbed on the non-crystalline silicon layer to the polysilicon layer, the arsenic ions may also diffuse into the substrate surrounding the deep trench. The substrate around the deep trench, as a result, also comprises the arsenic dopants. Therefore, in the subsequent definition of an active region, the active region may be shifted to the peripheral of the deep trench when a misalignment occurs. Since the channel region of the active region, which is positioned in the peripheral region of the deep trench, could have a high concentration of the arsenic dopants, the sub-threshold voltage of a subsequently formed gate is generated and the normal on-and-off of the device can not be operated. If a capacitor is to be fabricated according to the original dimension of the deep trench, and the problems related to the misalignment, when the active region is defined, are to be avoided, the overlay margin would become very small. In order to increase the overlay margin, one conventional approach is to reduce the dimension of the deep trench. However, the reduction of the deep trench would lead to the generation of the loading effect, which would limit the depth of the trench, and affect ultimately the capacity of the capacitor.